The present invention relates to a technique for testing complex digital circuits.
In the development of digital equipment, particularly computer and data processing equipment, circuit density has been increasing exponentially. This growth is attributed to the general advancement in semiconductor technology, in the computer sciences, and in the processes related to component miniaturization.
Since increases in chip circuit density are reflected in reduced costs per gate, cost reduction can be achieved by increasing the level of circuit integration; that is, by increasing the number of gate functions per chip. While this number has been increasing exponentially, the number of pins per chip has been increasing only approximately linearly. Inasmuch as the number of pins cannot be easily increased because of practical mechanical limitations, the number of gates per pin has also been increasing exponentially. Consequently, the accessability to internal nodes of integrated circuit chips is becoming increasingly difficult.
It is well known that test costs have been rising exponentially in correspondence with the aforementioned growing complexity and density of digital circuits. The ratio of test cost to total product cost has also been increasing with time. The testability of digital circuits is now receiving considerable attention because of the substantial economic impact of testing these circuits.
Studies have shown an order of magnitude increase in fault localization costs at various stages of testing. According to the report "Testability", by J. Turino, ATE Seminar, Pasadina, CA., January 1981., the cost of finding a single faulty component is approximately:
$0.05 at chip receiving test stations (sample testing), PA1 $0.50 at chip receiving test stations (100% testing), PA1 $5.00 at the printed circuit board level, PA1 $50.00 at the systems test level, and PA1 $500.00 in the field. PA1 (a) Moving fault localization to the earliest testing stage by considering it initially during the circuit design phase; and PA1 (b) Easing the testing and fault localization process to reduce the cost at each step. PA1 (1) forming the scan path shift register in the complex digital circuit; PA1 (2) clearing the scan path shift register; PA1 (3) applying a first digital test pattern to the primary inputs; PA1 (4) shifting the first digit of a second digital test pattern into the scan path shift register; PA1 (5) comparing the digits appearing at the primary outputs with those of a first digital number indicative of the proper operation of the circuit; PA1 (6) shifting the next digit of the second digital test pattern into the scan path shift register; PA1 (7) comparing the digits appearing at the primary outputs with those of another digital number indicative of the proper operation of the circuit; PA1 (8) repeating steps (6) and (7) for each successive digit of the second test pattern until all of the stages of the scan path shift register have been filled; and PA1 (9) producing a signal indicative of faulty circuit operation if the digits appearing at the primary outputs are not equal to those of the digital numbers to which they are compared.
Thus, the earlier in the manufacturing process that a fault can be found, the lower is the cost. Considerable research effort has therefore been directed to:
Since the methods of testing generation and simulation used thus far have, in many cases, reached the limit of their capability, suitable alternative testing approaches are being sought. One such approach is to design the network architecture and structure for easy testability during the circuit design phase. This approach is called "design for testability".
Using design for testability, significant test cost reduction is achieved by adding some additional hardware that transforms a circuit network, which is difficult to test into an easy to test one. This simplifies the test generation procedure (replacement of manual test generation by automatic test pattern generation systems), reduces simulation costs, reduces the number of test patterns, and therefore the costs of automatic test equipment.
Most structured design for testability practices are based on the concept that, if the state of all flip-flops can be controlled to any specific value, and if they can be observed with every straightforward operation, then test generation and a fault simulation can be reduced to that required for a combinational logic network. A control signal can switch the flip-flops from their normal mode of operation to a mode that makes them controllable and observable. Structures which permit such operation are known in the art as "scan structures".
For example, the U.S. Pat. No. 3,761,695 to Eichelberger discloses a testing technique for a digital circuit wherein internal storage elements (other than memory arrays), are connected such that they can also operate as shift registers and thus provide a so-called "scan path".
A scan path has two modes of operation: one which is the normal function mode, and a second which is a test mode wherein flip-flops of the circuit are interconnected into one long shift register called a "scan path". With the circuit in the test mode, it is possible to shift (load) an arbitrary test pattern into the flip-flops. By returning the circuit to its normal mode for one clock period, the remaining circuit acts upon the flip-flops' contents and primary input signals and stores the results in the scan flip-flops. If the circuit is then placed back into test mode, it is possible to shift out (unload) the contents of the scan flip-flops and compare these contents and the primary output signals with the appropriate correct values.
The n-th flip-flop in the shift register of the length k can be controlled after n (k.gtoreq.n) clock pulses.
If all flip-flops are included in a scan path, it is identified as a complete or full scan whereas, if some flip-flops are not included in the scan structure, it is identified as an incomplete or partial scan. A complete scan path assumes that all flip-flops of a circuit, except memory arrays (ROMs, RAMs, etc.), are included in the scan path. The remaining circuit outside of the scan path is purely combinational, and this allows very efficient execution of automatic test generator and fault simulation programs. An incomplete scan path assumes that a given number of flip-flops are not included in the scan path. Flip-flips that are easily controllable or observable are often omitted from the scan path leaving only the flip-flops in the scan path which cannot otherwise be tested.
The portion of the network that remains after removing the scan flip-flops will be subsequently referred to here as the "remaining portion" or "remainder of the network".
If the flip-flops outside of the incomplete scan path are asynchronous, then four typical configurations of the flip-flops can be identified with respect to the incomplete scan path. These four cases are illustrated in FIGS. 1A-1D, respectively. Asynchronous flip-flops are commonly used in many networks. In cases A or B the asynchronous flip-flops can be controlled only via primary inputs. These two configurations are called "optimal" (optimal incomplete scan path) because they can be treated as networks with a complete scan path. Fault detection takes place either on primary outputs (case A) or on scan path flip-flops (case B) whose contents must be shifted out.
Because the number of times the asynchronous flip-flops must be controlled and checked may exceed the number of times the scan path is loaded and unloaded, the configuration of case A is more favorable than the configuration of case B. When using an automatic tester, this means that the testing can be done faster in case A than in case B for networks of equal complexity and size.
If the asynchronous flip-flops external to the scan path are controlled by scan path flip-flops (FIGS. 1C and 1D) the overall network and the entire shift operation for pattern loading and unloading of the scan path must be simulated because the states of the asynchronous flip-flops may be influenced by the shifting of a test pattern through the scan path flip-flops. Such a configuration is therefore called "non-optimal" (non-optimally implemented incomplete scan path).
The problem with a non-optimal, incomplete scan path network is that the states of the asynchronous flip-flops are influenced by the application of a test pattern to scan flip-flops such that, unless the overall network and the applied test pattern are simulated, it is not possible to determine the states of the asynchronous flip-flops with full certainty. This is particularly true of the remaining portion of networks with a sequential depth greater than one. This makes it necessary to proceed differently for modeling and for test generation. Although ATG can still be confined to the remaining portion of the network, the resulting patterns must be verified at the level of the overall network by fault simulation.
A characteristic of a non-optimal incomplete scan path is that the loading of test patterns must be simulated. The loading of a test pattern into an incomplete scan path can be seen as the application of test patterns which are similar to "pseudorandom" test patterns on the inputs of the remaining circuit. In other words these patterns detect faults in the remainder of the network only by chance.